Regviz

Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B520F2048IQ100 /SMU /PPUPATD1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PPUPATD1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/Series1/EFM32GG11B/EFM32GG11B520F2048IQ100/SMU/PPUPATD1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PCNT0)PCNT0 0 (PCNT1)PCNT1 0 (PCNT2)PCNT2 0 (RMU)RMU 0 (RTC)RTC 0 (RTCC)RTCC 0 (SMU)SMU 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TIMER2)TIMER2 0 (TIMER3)TIMER3 0 (TIMER4)TIMER4 0 (TIMER5)TIMER5 0 (TIMER6)TIMER6 0 (TRNG0)TRNG0 0 (UART0)UART0 0 (UART1)UART1 0 (USART0)USART0 0 (USART1)USART1 0 (USART2)USART2 0 (USART3)USART3 0 (USART4)USART4 0 (USART5)USART5 0 (WDOG0)WDOG0 0 (WDOG1)WDOG1 0 (WTIMER0)WTIMER0 0 (WTIMER1)WTIMER1 0 (WTIMER2)WTIMER2 0 (WTIMER3)WTIMER3

Description

PPU Privilege Access Type Descriptor 1

Fields

PCNT0

Pulse Counter 0 access control bit
PCNT1

Pulse Counter 1 access control bit
PCNT2

Pulse Counter 2 access control bit
RMU

Reset Management Unit access control bit
RTC

Real-Time Counter access control bit
RTCC

Real-Time Counter and Calendar access control bit
SMU

Security Management Unit access control bit
TIMER0

Timer 0 access control bit
TIMER1

Timer 1 access control bit
TIMER2

Timer 2 access control bit
TIMER3

Timer 3 access control bit
TIMER4

Timer 4 access control bit
TIMER5

Timer 5 access control bit
TIMER6

Timer 6 access control bit
TRNG0

True Random Number Generator 0 access control bit
UART0

Universal Asynchronous Receiver/Transmitter 0 access control bit
UART1

Universal Asynchronous Receiver/Transmitter 1 access control bit
USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit
USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit
USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit
USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit
USART4

Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit
USART5

Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit
WDOG0

Watchdog access control bit
WDOG1

Watchdog access control bit
WTIMER0

Wide Timer 0 access control bit
WTIMER1

Wide Timer 0 access control bit
WTIMER2

Wide Timer 2 access control bit
WTIMER3

Wide Timer 3 access control bit

Links

()

Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data